Integrated circuits may be fabricated on silicon-on-insulator (SOI) substrates (as compared with bulk silicon substrates) to achieve higher device speeds and/or lower power dissipation. The SOI structure comprises a silicon substrate, a buried dielectric layer (for example, silicon dioxide) and a relatively thin (e.g., sub-micron) single crystal silicon surface layer, where this surface layer is typically referred to as the “SOI” layer.
In the optical regime, an SOI layer can be used as the waveguiding layer for infrared wavelengths (1.1 μm-5.0 μm) for which silicon is nearly transparent. By forming reflecting, confining or transmitting boundaries in the waveguiding layers, passive optical devices (e.g., mirrors, rib waveguides, lenses, gratings, etc.) can be realized. In addition, the same free carriers (electrons and holes) that are used for the electronic functionality in integrated circuits can be used to actively manipulate light in silicon. The injection or removal of free carriers in silicon affects both the real and imaginary index of the waveguide and causes a phase shift/absorption of the light traveling through the waveguide. When properly designed and combined with the confinement of light in a silicon waveguide, an electronic device can modify the optical properties of the waveguide, thus affecting the optical mode. As a result, SOI technology offers a powerful platform for the monolithic integration of electrical, passive optical and active electro-optical devices on a single substrate.
In order to leverage the infrastructure and expertise that has been developed for the fabrication of electronic devices in an SOI platform, passive optical and active electro-optical devices must be fabricated using the same thin SOI layer that is used for fabricating electronic devices. Hence, the ability to efficiently couple light into a relatively thin SOI layer, guide light with low loss and achieve active manipulation (i.e., modulation and detection) of light at high speeds needs to be accomplished without significantly affecting the performance of the conventional electronic circuits. To enable leveraging of the investment, infrastructure and discipline in the developed silicon integrated circuit industry, the device structure and fabrication methods for optical and electro-optical devices must be compatible with the advancements in the integrated circuit industry.
For realization of high performance, SOI-based electronic devices, several device architectures (e.g., partially-depleted CMOS, fully-depleted CMOS, BiCMOS, etc.) are well-known in the art and are currently being used in high volume production of advanced integrated circuits.
FIG. 1 illustrates an exemplary prior art SOI-based CMOS device 10. As is well known, a CMOS device contains a PMOS (P-channel) transistor 12 and an NMOS (N-channel) transistor 14. The SOI structure comprises a silicon substrate 16, a buried dielectric layer 18 and a relatively thin SOI layer 20. Electrical isolation between PMOS transistor 12 and NMOS transistor 14 is achieved by removing the portions of SOI layer 20 in the non-transistor areas, and filling these areas with a dielectric insulation material, illustrated as dielectric insulating region 22 in FIG. 1.
In a conventional prior art CMOS process, the transistors may be typically formed using the following exemplary processing steps:                Doping active regions of SOI layer 20 with appropriate doping type and profile to form the body region and channel region for each device, illustrated as n-type body region 24 and p-channel region 26 for PMOS transistor 12 and p-type body region 28 and n-channel region 30 for NMOS transistor 14.        Forming a thin gate dielectric layer to cover channel regions 26 and 30, where if an oxide is used, a thermal process in employed to grow the layer, the dielectric layer forming a PMOS transistor gate dielectric 34 and an NMOS transistor gate dielectric 36.        Depositing, doping and patterning a silicon (typically in the form of polysilicon) layer to form a PMOS transistor gate region 38 and an NMOS transistor gate region 40.        Forming sidewall spacers 42 and 44 on either side of PMOS transistor gate region 38, and sidewall spacers 46 and 48 on either side of NMOS transistor gate region 40.        Forming self-aligned source and drain regions (by virtue of the sidewall spacers), using photolithography/ion implantation, forming p+ drain and source regions 50 and 52 for PMOS transistor 12 and n+ drain and source regions 54 and 56 for NMOS transistor 14.        Forming silicide on the electrical contact areas, illustrated as silicide contacts 58, 60 and 62 for PMOS transistor 12 and silicide contacts 64, 66 and 68 for NMOS transistor 14.        Forming final contact and multi-level metallization structures (illustrated in FIG. 4 and discussed hereinbelow).        
It is to be noted that the above process description is considered to be exemplary only, showing a commonly used NMOS and PMOS transistor device structure (the basic elements used in CMOS technology) and a generalized processing sequence for making the CMOS device. Depending upon the technology (CMOS, BiCMOS, etc.) and the fabrication facility being used, a large variety of transistor structures can be fabricated using several different processing sequences.
In MOS transistors, a channel region (such as channel regions 26 and 30 in FIG. 1) is formed by applying appropriate voltages to the silicide contacts of the source, drain and gate regions of the transistor. The conductance of the channel region, and thus the current flowing between the source and the drain is modulated by modulating the gate voltage. In order to minimize the resistance associated with the gate region, the polysilicon material is heavily doped with appropriate impurities to achieve “metal-like” electrical properties.
The prior art describes fabrication of electro-optic devices using a relatively thick SOI layer (e.g., a few microns thick). Use of a thick SOI layer limits the optical waveguide and electro-optic devices to be multi-mode, making it difficult to optimally use the free carrier-based electro-optic effect for manipulation of light. Further, due to the bulk-like silicon region formed in the thick SOI layer, the high speed and low power aspects of conventional SOI CMOS electronics cannot be achieved. In addition, low resolution, non-conventional processes such as Deep reactive ion etching (RIE) are needed for definition of optical devices, and the resultant topology limits the use of conventional planarization and multi-level metallization processes, further limiting the realization of high performance electronics in combination with electro-optic devices on the same substrate.